Yeh-Jen Huang

According to our database1, Yeh-Jen Huang authored at least 5 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

2008
2010
2012
2014
2016
2018
2020
2022
2024
0
1
2
1
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

2022
Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2015
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2009
Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


  Loading...