Yean-Ru Chen

Orcid: 0000-0003-4841-4838

According to our database1, Yean-Ru Chen authored at least 24 papers between 2005 and 2024.

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Bibliography

2024
Markov Clustering-Based Content Placement in Roadside-Unit Caching With Deadline Constraint.
IEEE Trans. Intell. Transp. Syst., September, 2024

Robustness Analysis of Neural Network Designs with Sparsity Investigation.
J. Inf. Sci. Eng., May, 2024

A Parallel and Distributed Quantum SAT Solver Based on Entanglement and Teleportation.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2024

2023
SMT Solver With Hardware Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Empirical study on security verification and assessment of neural network accelerator.
Microprocess. Microsystems, June, 2023

A Parallel and Distributed Quantum SAT Solver Based on Entanglement and Quantum Teleportation.
CoRR, 2023

A Quantum SMT Solver for Bit-Vector Theory.
CoRR, 2023

2022
A Study on Traffic Asymmetry for Detecting DDoS Attack in P4-based SDN.
J. Inf. Sci. Eng., 2022

Robustness Analysis of Neural Network Designs for ReLU Family and Batch Normalization.
Proceedings of the International Conference on Technologies and Applications of Artificial Intelligence, 2022

Empirical Study of Proposed Meltdown Attack Implementation on BOOM v3.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2014
Accelerating Coverage Estimation Through Partial Model Checking.
IEEE Trans. Computers, 2014

Unified Security and Safety Risk Assessment - A Case Study on Nuclear Power Plant.
Proceedings of the 2014 International Conference on Trustworthy Systems and their Applications, 2014

2013
Backward probing deadlock detection for networks-on-chip.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

2012
Congestion-aware scheduling for NoC-based reconfigurable systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
VERTAF/Multi-Core: A SysML-Based Application Framework for Multi-Core Embedded Software Development.
J. Comput. Sci. Technol., 2011

2009
Modeling and verification of real-time embedded systems with urgency.
J. Syst. Softw., 2009

Model-driven development of multi-core embedded software.
Proceedings of the 2009 ICSE Workshop on Multicore Software Engineering, 2009

VERTAF/Multi-Core: A SysML-Based Application Framework for Multi-Core Embedded Software Development.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2009

Compositional Automata Reduction with Non-critical Path Slicing.
Proceedings of the 2009 International Conference on Foundations of Computer Science, 2009

2007
Model Checking Safety-Critical Systems Using Safecharts.
IEEE Trans. Computers, 2007

Automatic Failure Analysis Using Safecharts.
Int. J. Softw. Eng. Knowl. Eng., 2007

Modeling and Automatic Failure Analysis of Safety-Critical Systems Using Extended Safecharts.
Proceedings of the Computer Safety, 2007

2006
Model Checking Timed Systems with Urgencies.
Proceedings of the Automated Technology for Verification and Analysis, 2006

2005
Model Checking Prioritized Timed Automata.
Proceedings of the Automated Technology for Verification and Analysis, 2005


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