Ye-Sing Luo

According to our database, Ye-Sing Luo authored at least 5 papers between 2013 and 2018.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2018

A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control.

Ye-Sing Luo, Hsing-Hung Lin, Shen-Iuan Liu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

A Voltage Multiplier With Adaptive Threshold Voltage Compensation.

Ye-Sing Luo, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2017

2014

A low-input-swing AC-DC voltage multiplier using Schottky diodes.

Ye-Sing Luo, Shen-Iuan Liu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

Ultrasonic Power/Data Telemetry and Neural Stimulator With OOK-PM Signaling.

Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Ultrasonic telemetry and neural stimulator with FSK-PWM signaling.

Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, I-Chin Wu, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013