Ye-Dam Kim

Orcid: 0000-0001-7497-1932

Affiliations:
  • KAIST, Yuseong-gu, Daejeon, South Korea


According to our database1, Ye-Dam Kim authored at least 16 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling.
IEEE J. Solid State Circuits, October, 2024

A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC.
IEEE J. Solid State Circuits, August, 2024

A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3<sup>rd</sup>-Order Noise Coupling.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023
An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3<sup>rd</sup>-Order SAR-Assisted CT DSM with 1-0 MASH and DNC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
A 4<sup>th</sup>-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS.
IEEE J. Solid State Circuits, 2021

A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability.
IEEE J. Solid State Circuits, 2020

An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018


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