Yazhou Zu
Orcid: 0000-0003-0047-6976
According to our database1,
Yazhou Zu
authored at least 16 papers
between 2013 and 2024.
Collaborative distances:
Collaborative distances:
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On csauthors.net:
Bibliography
2024
Proceedings of the 21st USENIX Symposium on Networked Systems Design and Implementation, 2024
2021
Erratum to "Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
2020
Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
Fine-Tuning the Active Timing Margin (ATM) Control Loop for Maximizing Multi-core Efficiency on an IBM POWER Server.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Efficient and reliable power delivery in voltage-stacked manycore system with hybrid charge-recycling regulators.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
2013
Proceedings of the 19th IEEE International Conference on Parallel and Distributed Systems, 2013