Yazheng Tu
Orcid: 0000-0002-1624-9500
According to our database1,
Yazheng Tu
authored at least 14 papers
between 2022 and 2025.
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Bibliography
2025
HSPA: High-Throughput Sparse Polynomial Multiplication for Code-based Post-Quantum Cryptography.
ACM Trans. Embed. Comput. Syst., January, 2025
LTE: Lightweight and Timing-Efficient Unequal-Sized Polynomial Multiplication Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025
2024
IEEE Comput. Archit. Lett., 2024
2023
KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication.
IEEE Comput. Archit. Lett., 2023
LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
2022
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Comput. Archit. Lett., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022