Yasuyuki Matsuya

According to our database, Yasuyuki Matsuya authored at least 13 papers between 1989 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A Method for Detecting Timing of Photodiode Saturation without In-Pixel TDC for High-Dynamic-Range CMOS Image Sensor.

Yuji Inagaki, Yasuyuki Matsuya

IEICE Trans. Electron., 2021

2017

A Logarithmic Compression ADC Using Transient Response of a Comparator.

Yuji Inagaki, Yusaku Sugimori, Eri Ioka, Yasuyuki Matsuya

IEICE Trans. Electron., 2017

2016

Noise Characteristic of the Chaotic Double Loop Delta Sigma Modulator.

Eri Ioka, Nozomi Watanabe, Ryo Makishima, Yasuyuki Matsuya

Int. J. Bifurc. Chaos, 2016

2015

Causal analysis between vehicle operating data and physiological responses.

Shizuka Bando, Akio Nozawa, Yasuyuki Matsuya

Artif. Life Robotics, 2015

2011

FOREWORD.

Yasuyuki Matsuya

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2009

A Stereo Transmission Technique Using PDM Data and Synchronized Clock Channels.

Yasuyuki Matsuya, Takahiro Mesuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2005

A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks.

Jun Terada, Yasuyuki Matsuya, Shin'ichiro Mutoh, Yuichi Kado

IEICE Trans. Electron., 2005

2003

8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region.

Jun Terada, Yasuyuki Matsuya, Fumiharu Morisawa, Yuichi Kado

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

1997

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits.

Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada

IEEE J. Solid State Circuits, 1997

1996

A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application.

Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada

IEEE J. Solid State Circuits, 1996

1995

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS.

Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada

IEEE J. Solid State Circuits, August, 1995

1994

1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping.

Yasuyuki Matsuya, Junzo Yamada

IEEE J. Solid State Circuits, December, 1994

1989

A 17 bit oversampling D-A conversion technology using multistage noise shaping.

Yasuyuki Matsuya, Kuniharu Uchimura, Atsushi Iwata, Takao Kaneko

IEEE J. Solid State Circuits, August, 1989