Yasutaka Horiba

According to our database, Yasutaka Horiba authored at least 6 papers between 1988 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design.

Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba

IEICE Trans. Electron., 2006

2005

A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures.

Toshiki Kanamoto, Tetsuya Watanabe, Mitsutoshi Shirota, Masayuki Terai, Tatsuya Kunikiyo, Kiyoshi Ishikawa, Yoshihide Ajioka, Yasutaka Horiba

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2001

A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree.

Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba

IEEE J. Solid State Circuits, 2001

1999

The D30V/MPEG multimedia processor.

Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba

IEEE Micro, 1999

1988

An SOI structure for flash A/D converter.

Toshio Kumamoto, Masao Nakaya, Shigeru Kusunoki, Tadashi Nishimura, Nobuharu Yazawa, Yoichi Akasaka, Yasutaka Horiba

IEEE J. Solid State Circuits, February, 1988

A DSP line equalizer VLSI for TCM digital subscriber-line transmission.

Hideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba

IEEE J. Solid State Circuits, February, 1988