Yasushi Yuminaka

According to our database, Yasushi Yuminaka authored at least 45 papers between 1991 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Evaluating PAM-4 Data Transmission Quality Using Multi-Dimensional Mapping of Received Symbols.

Yasushi Yuminaka, Kazuharu Nakajima, Yosuke Iijima

IEICE Trans. Inf. Syst., 2024

Foreword.

Yasushi Yuminaka

IEICE Trans. Inf. Syst., 2024

Evaluation of Multi-Valued Data Transmission in Two-Dimensional Symbol Mapping using Linear Mixture Model.

Yosuke Iijima, Atsunori Okada, Yasushi Yuminaka

IEICE Trans. Inf. Syst., 2024

Specialized Waveform Equalization Techniques for Multi-Valued Data Transmission.

Yasushi Yuminaka, Hayate Hasegawa, Nagito Ishida, Yosuke Iijima

Proceedings of the 54th IEEE International Symposium on Multiple-Valued Logic, 2024

Equalization for Compensation of Intersymbol Relationship of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping.

Yosuke Iijima, Atsunori Okada, Yasushi Yuminaka

Proceedings of the 54th IEEE International Symposium on Multiple-Valued Logic, 2024

Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing.

Satoshi Moriya, Hideaki Yamamoto, Masaya Ishikawa, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato

Proceedings of the International Joint Conference on Neural Networks, 2024

2023

Multi-Valued Data Transmission Quality Evaluation Using Two-Dimensional PAM-4 Symbol Mapping.

Kazuharu Nakajima, Yasushi Yuminaka, Yosuke Iijima

FLAP, 2023

PAM-4 Data Transmission Quality Evaluation Using Two- and Three-Dimensional Mapping of Received Symbols.

Yasushi Yuminaka, Kazuharu Nakajima, Yosuke Iijima

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

Evaluation and Symbol Classification of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping with Linear Mixture Model.

Yosuke Iijima, Kazuharu Nakajima, Yasushi Yuminaka

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

2022

Efficient PAM-4 Symbol Estimation Using Soft Clustering.

Yosuke Iijima, Yasushi Yuminaka

FLAP, 2022

Two-Dimensional Symbol Mapping for Evaluating Multi-Valued Data Transmission Quality.

Yosuke Iijima, Kazuharu Nakajima, Yasushi Yuminaka

Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation.

Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas

Proceedings of the International Joint Conference on Neural Networks, 2022

2021

PAM-4 Eye-Opening Monitor Technique Using Gaussian Mixture Model for Adaptive Equalization.

Yosuke Iijima, Keigo Taya, Yasushi Yuminaka

IEICE Trans. Inf. Syst., 2021

Efficient PAM-4 Data Transmission with Closed Eye Using Symbol Distribution Estimation.

Yosuke Iijima, Yasushi Yuminaka

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model.

Shigeo Sato, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto, Yoshihiko Horio, Yasushi Yuminaka, Jordi Madrenas

Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021

2020

PAM-4 Signal Transmitter using FPGA and DAC for Serial-link Test.

Yasushi Yuminaka, Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima

FLAP, 2020

Statistical Waveform Evaluation Method for Adaptive PAM-4 Equalization.

Keigo Taya, Yasushi Yuminaka, Yosuke Iijama

FLAP, 2020

PAM-4 Eye-Opening Monitoring Techniques Using Gaussian Mixture Model.

Yosuke Iijima, Keigo Taya, Yasushi Yuminaka

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

2019

Waveform Shaping Transmitter Combining Digital and Analog Circuits for Multi - Valued Signaling.

Yosuke Iijima, Yasushi Yuminaka

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

2018

Multi-valued Signal Generation and Measurement for PAM-4 Serial-Link Test.

Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima, Yasushi Yuminaka

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017

Double-Rate Tomlinson-Harashima Precoding for Multi-Valued Data Transmission.

Yosuke Iijima, Yasushi Yuminaka

IEICE Trans. Inf. Syst., 2017

PAM-4 Eye Diagram Analysis and Its Monitoring Technique for Adaptive Pre-Emphasis for Multi-valued Data Transmissions.

Yasushi Yuminaka, Takuya Kitamura, Yosuke Iijima

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

2016

Comparison of Spectrally Efficient Coding Techniques for High-Speed VLSI Data Transmission.

Yasushi Yuminaka, Yuuki Takada, Tomonao Okada

J. Multiple Valued Log. Soft Comput., 2016

Multiple-Valued Signaling for High-Speed Serial Links Using Tomlinson-Harashima Precoding.

Yasushi Yuminaka, Yosuke Iijima

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Double-Rate Equalization Using Tomlinson-Harashima Precoding for Multi-valued Data Transmission.

Yosuke Iijima, Yasushi Yuminaka

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2014

High-Speed Interconnection for VLSI Systems Using Multiple-Valued Signaling with Tomlinson-Harashima Precoding.

Yosuke Iijima, Yuki Takada, Yasushi Yuminaka

IEICE Trans. Inf. Syst., 2014

Comparison of Spectrally Efficient Coding Techniques for High-Speed Serial Links.

Yasushi Yuminaka, Yuki Takada, Tomonao Okada, Yosuke Iijima

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Evaluation of High-Speed Interfaces for VLSI Systems Using Tomlinson-Harashima Precoding.

Yosuke Iijima, Yasushi Yuminaka

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

2012

A Bandwidth-Efficient Ternary Signaling Scheme for 1-D Partial-Response Channels.

Yasushi Yuminaka, Kyohei Kawano

J. Multiple Valued Log. Soft Comput., 2012

Efficient Data Transmission Using Multiple-Valued Pulse-Position Modulation.

Yasushi Yuminaka, Masaaki Okui

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

2010

Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques.

Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi

IEICE Trans. Inf. Syst., 2010

A Ternary Partial-Response Signaling Scheme for Capacitively Coupled Interface.

Yasushi Yuminaka, Kyohei Kawano

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

2009

Time-Domain Pre-Emphasis Techniques for Multiple Valued Data Transmission.

Yasushi Yuminaka, Yasunori Takahashi

J. Multiple Valued Log. Soft Comput., 2009

Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects.

Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi

Proceedings of the ISMVL 2009, 2009

2008

Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data.

Yasushi Yuminaka, Yasunori Takahashi

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

2007

Equalization Techniques for Multiple-Valued Data Transmission and Their Application.

Yasushi Yuminaka, Kazuyoshi Yamamura

J. Multiple Valued Log. Soft Comput., 2007

2005

Intra/Inter-Chip CDMA Communications for Efficient Data Transmission Towards New Paradigm of Computing.

Yasushi Yuminaka

J. Multiple Valued Log. Soft Comput., 2005

2002

Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI.

Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2000

An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access.

Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1999

A high-speed CMOS track/hold circuit.

Mohd Asmawi Mohamed Zin, Haruo Kobayashi, Kazuya Kobayashi, Jun-ichi Ichimura, Hao San, Yoshitaka Onaya, Yasuyuki Kimura, Yasushi Yuminaka, Yoshisato Sasaki, Kouji Tanaka, Fuminori Abe

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences.

Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1996

Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves.

Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1994

Design of Wave-Parallel Computing Circuits for Densely Connected Architectures.

Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1993

Design of Set-Valued Logic Networks for Wave-Parallel Computing.

Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

1991

Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing.

Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991