Yasushi Terada
According to our database1,
Yasushi Terada
authored at least 6 papers
between 1988 and 1994.
Collaborative distances:
Collaborative distances:
Timeline
1988
1989
1990
1991
1992
1993
1994
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1
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3
1
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
1994
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.
IEEE J. Solid State Circuits, April, 1994
1992
A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories.
IEEE J. Solid State Circuits, April, 1992
1990
IEEE J. Solid State Circuits, February, 1990
1989
IEEE J. Solid State Circuits, October, 1989
IEEE J. Solid State Circuits, August, 1989
1988
IEEE J. Solid State Circuits, February, 1988