Yasuro Yamane

According to our database, Yasuro Yamane authored at least 3 papers between 2002 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Low-power InP-HEMT switch ICs integrating miniaturized 2×2 switches for 10-Gb/s systems.

Hideki Kamitsuna, Yasuro Yamane, Masami Tokumitsu, Hirohiko Sugahara, Masahiro Muraguchi

IEEE J. Solid State Circuits, 2006

2004

Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/s.

Hiroyuki Fukuyama, Kimikazu Sano, Koichi Murata, Hiroto Kitabayashi, Yasuro Yamane, Takatomo Enoki, Hirohiko Sugahara

IEEE J. Solid State Circuits, 2004

2002

Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors.

Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki

IEEE J. Solid State Circuits, 2002