Yasuo Sugure

According to our database, Yasuo Sugure authored at least 4 papers between 2006 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme.

Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2015

2014

A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM.

Go Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the ARCS 2014, 2014

2011

Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units.

Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

2006

Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications.

Yasuo Sugure, Seiji Takeuchi, Yuichi Abe, Hiromichi Yamada, Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka, Takanori Shimura

IEICE Trans. Electron., 2006