Yasuo Itoh

According to our database, Yasuo Itoh authored at least 16 papers between 1983 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving.

Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, Yasunori Tanaka

IEEE J. Solid State Circuits, 2014

2008

Relationship between fractal dimension and favorability of facial imagery.

Mayumi Oyama-Higa, Tiejun Miao, Yasuo Itoh

Int. J. Hybrid Intell. Syst., 2008

Is the perceived agreeability of a face related to the fractal dimension of the face?

Yasuo Itoh, Mayumi Oyama-Higa, Tiejun Miao

Proceedings of the IEEE International Conference on Systems, 2008

2007

Does the transition of the interval in perceptional alternation have a chaotic rhythm?

Yasuo Itoh, Mayumi Oyama

Proceedings of the IEEE International Conference on Systems, 2007

2006

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.

Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada

IEICE Trans. Electron., 2006

2001

A 76-mm² 8-Mb chain ferroelectric memory.

Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki

IEEE J. Solid State Circuits, 2001

2000

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.

Ryu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka

IEEE J. Solid State Circuits, 2000

1997

A 120-mm² 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed.

Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto

IEEE J. Solid State Circuits, 1997

1995

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM.

Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto

IEEE J. Solid State Circuits, November, 1995

1991

A 4 Mb NAND EEPROM with tight programmed V_t distribution.

Masaki Momodomi, Tomoharu Tanaka, Yoshihisa Iwata, Yoshiyuki Tanaka, Hideko Oodaira, Yasuo Itoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, April, 1991

1990

A high-density NAND EEPROM with block-page programming for microcomputer applications.

Yoshihisa Iwata, Masaki Momodomi, Tomoharu Tanaka, Hideko Oodaira, Yasuo Itoh, Ryozo Nakayama, Ryouhei Kirisawa, Seiichi Aritome, Tetsuo Endoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, April, 1990

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC.

Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka

IEEE J. Solid State Circuits, February, 1990

1989

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell.

Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka

IEEE J. Solid State Circuits, October, 1989

New nibbled-page architecture for high-density DRAMs.

Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi

IEEE J. Solid State Circuits, August, 1989

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.

Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, June, 1989

1983

An adaptive echo canceller using digital signal processor LSI chips.

Kazunori Ozawa, Takashi Araseki, Yasuo Itoh

Proceedings of the IEEE International Conference on Acoustics, 1983