Yasuo Hidaka

According to our database, Yasuo Hidaka authored at least 12 papers between 1991 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters.

Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon

IEEE J. Solid State Circuits, 2013

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS.

Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE.

Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS.

Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel.

Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control.

Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone

IEEE J. Solid State Circuits, 2009

A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control.

Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.

Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Design Consideration of 6.25 Gbps Signaling for High-Performance Server.

Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

1994

Architecture of parallel management kernel for PIE64.

Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka

Future Gener. Comput. Syst., 1994

1993

Multiple Threads in Cyclic Register Windows.

Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka

Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

1991

A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages.

Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka

Proceedings of the Logic Programming, Proceedings of the 1991 International Symposium, San Diego, California, USA, Oct. 28, 1991