Yasunao Katayama

Orcid: 0000-0002-2674-9365

According to our database1, Yasunao Katayama authored at least 34 papers between 1989 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2020
Spatially Arranged Sparse Recurrent Neural Networks for Energy Efficient Associative Memory.
IEEE Trans. Neural Networks Learn. Syst., 2020

2019
Like Quantum Computing without Quantum Physics: Is it How the Brain Works?
CoRR, 2019

Channel Model for Spiking Neural Networks Inspired by Impulse Radio MIMO Transmission.
Proceedings of the 2019 IEEE Global Communications Conference, 2019

2017
Brain-Inspired Memory Architecture for Sparse Nonlocal and Unstructured Workloads.
Proceedings of the Computing Frontiers Conference, 2017

2015
Wave-based device scaling concept for brain-like energy efficiency and integration.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Regularity and randomness in modular network structures for neural associative memories.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

Wave-Based Reservoir Computing by Synchronization of Coupled Oscillators.
Proceedings of the Neural Information Processing - 22nd International Conference, 2015

Single-channel full-duplex mmWave link using phased-array for Ethernet.
Proceedings of the 12th Annual IEEE Consumer Communications and Networking Conference, 2015

2014
60-GHz single-carrier coherent detection system with robust 16-QAM signal recovery.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

An Energy-Efficient Computing Approach by Filling the Connectome Gap.
Proceedings of the Unconventional Computation and Natural Computation, 2014

Non-intrusive Scalable Memory Access Tracer.
Proceedings of the Quantitative Evaluation of Systems - 11th International Conference, 2014

Hopfield-Type Associative Memory with Sparse Modular Networks.
Proceedings of the Neural Information Processing - 21st International Conference, 2014

2013
Software-defined massive multicore networking via freespace optical interconnect.
Proceedings of the Computing Frontiers Conference, 2013

2012
MIMO link design strategy for wireless data center applications.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012

An effective initialization of interference cancellation algorithms for distributed MIMO systems in wireless datacenters.
Proceedings of the 2012 IEEE Global Communications Conference, 2012

Multimedia content-downloading system using millimeter-wave attached memory.
Proceedings of the 2012 IEEE Consumer Communications and Networking Conference (CCNC), 2012

2011
Wireless data center networking with steered-beam mmWave links.
Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

Instant multimedia contents downloading system using a 60-GHZ-2.4-GHZ hybrid wireless link.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

Multi-Gbps 60-GHz single-carrier system using a low-power coherent detection technique.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

Universal optical multi-drop bus for heterogeneous memory architecture.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2008
Multi-Gbps wireless systems over 60-GHz SiGe radio link with BW-efficient noncoherent detections.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

2007
Optical Interconnect Opportunities for Future Server Memory Systems.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2-Gbps Uncompressed HDTV Transmission over 60-GHz SiGe Radio Link.
Proceedings of the 4th IEEE Consumer Communications and Networking Conference, 2007

2006
Multiple-Packet Recovery Technique using Partially-Overlapped Block Codes.
Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006

2003
Bit error rate analysis on iterative two-stage decoding of two dimensional codes by importance sampling.
Proceedings of IEEE International Conference on Communications, 2003

An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2001
Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2<sup>m</sup>).
Proceedings of the Computer Aided Verification, 13th International Conference, 2001

2000
One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems.
Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000

Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder.
Proceedings of the IEEE International Conference On Computer Design, 1999

Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1997
Trends in semiconductor memories.
IEEE Micro, 1997

Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1989
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing.
IEEE J. Solid State Circuits, October, 1989


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