Yasumoto Tomita

According to our database, Yasumoto Tomita authored at least 20 papers between 2005 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Acceleration of Structural Analysis Simulations using CNN-based Auto-Tuning of Solver Tolerance.

Amir Haderbache, Koichi Shirahata, Takuji Yamamoto, Yasumoto Tomita, Hiroshi Okuda

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2018

An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors.

Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita

IEEE J. Solid State Circuits, 2018

GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning.

Koichi Shirahata, Youri Coppens, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike

Int. J. Netw. Comput., 2018

Speed-Up of Object Detection Neural Network with GPU.

Takuya Fukagai, Kyosuke Maeda, Satoshi Tanabe, Koichi Shirahata, Yasumoto Tomita, Atsushi Ike, Akira Nakagawa

Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

2017

An automated CNN recommendation system for image classification tasks.

Song Wang, Li Sun, Wei Fan, Jun Sun, Satoshi Naoi, Koichi Shirahata, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike, Tetsutaro Hashimoto

Proceedings of the 2017 IEEE International Conference on Multimedia and Expo, 2017

2016

An Automated CNN Recommendation System for Image Classification Tasks.

Song Wang, Li Sun, Wei Fan, Jun Sun, Satoshi Naoi, Koichi Shirahata, Takuya Fukagai, Yasumoto Tomita, Atsushi Ike

CoRR, 2016

An FPGA-accelerated partial duplicate image retrieval engine for a document search system.

Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, Yasumoto Tomita, Takayuki Baba, Yasuhiro Watanabe

Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision, 2016

An FPGA-accelerated partial image matching engine for massive media data searching systems.

Takashi Shimizu, Yasumoto Tomita, Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, David Thach, Takashi Miyoshi, Takayuki Baba, Yasuhiro Watanabe, Atsushi Ike

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Memory reduction method for deep neural network training.

Koichi Shirahata, Yasumoto Tomita, Atsushi Ike

Proceedings of the 26th IEEE International Workshop on Machine Learning for Signal Processing, 2016

2014

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.

Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

What is a good way to expand a silicon value to a solution value?

Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2010

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.

Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2010

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.

Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.

Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda

IEICE Trans. Electron., 2010

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.

Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.

Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.

Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.

Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2007

2006

A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid.

Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS.

Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2005