Yasumitsu Orii

According to our database1, Yasumitsu Orii authored at least 12 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Semiconductor Packaging Revolution in the Era of Chiplets : Keynote 1.
Proceedings of the IEEE International Test Conference in Asia, 2023

Semiconductor Packaging Revolution in the Era of Chiplets.
Proceedings of the International Conference on IC Design and Technology, 2023

2020
Molecular Inverse-Design Platform for Material Industries.
Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020

2019
An Information Extraction and Knowledge Graph Platform for Accelerating Biochemical Discoveries.
CoRR, 2019

2015
Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Thermo-mechanical evaluation of 3D packages.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011
Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Combination between the nonlinear finite element analyses and the strain measurement using the digital image correlation for a new 3D SIC package.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
High density 3D integration by pre-applied Inter Chip Fill.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2004
Solder joint reliability evaluation of chip scale package using a modified Coffin-Manson equation.
Microelectron. Reliab., 2004


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