Yasumitsu Murai

According to our database, Yasumitsu Murai authored at least 3 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm² Density With Charge-Assisted Offset Cancellation Sense Amplifier.

Masaya Nakano, Yoshinobu Kaneda, Satoru Nakanishi, Yasumitsu Murai, Yosuke Tashiro, Yasuhiko Taito, Tomoya Ogawa, Hidenori Mitani, Takashi Ito, Takashi Kono

IEEE J. Solid State Circuits, 2022

2019

A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications.

Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka

IEICE Trans. Electron., 2019

2018

Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications.

Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda, Hiroyuki Kondo

IEEE Trans. Multi Scale Comput. Syst., 2018