Yasumi Nakamura

According to our database1, Yasumi Nakamura authored at least 3 papers between 2008 and 2011.

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Bibliography

2011
Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout.
IEICE Trans. Electron., 2011

2009
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise.
IEICE Trans. Electron., 2009

2008
1/5 power reduction by global optimization based on fine-grained body biasing.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008


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