Yasumasa Nishimura

According to our database, Yasumasa Nishimura authored at least 5 papers between 1984 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2004

Open architecture tester: what is a key issue of OAT?

Yasumasa Nishimura

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

1996

A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond.

Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami

IEEE J. Solid State Circuits, 1996

1989

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode.

Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima

IEEE J. Solid State Circuits, February, 1989

1986

Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.

Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka

Proceedings of the Proceedings International Test Conference 1986, 1986

1984

A New Timing Calibration Method for High Speed Memory Test.

Yasumasa Nishimura, Mitsuhiro Hamada, Y. Hayasaka

Proceedings of the Proceedings International Test Conference 1984, 1984