Yasumasa Nishimura

According to our database1, Yasumasa Nishimura authored at least 7 papers between 1984 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

1985
1990
1995
2000
0
1
2
1
1
1
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2004
Open architecture tester: what is a key issue of OAT?
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

1996
A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond.
IEEE J. Solid State Circuits, 1996

1993
A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's.
IEEE J. Solid State Circuits, November, 1993

1990
A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture.
IEEE J. Solid State Circuits, October, 1990

1989
A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode.
IEEE J. Solid State Circuits, February, 1989

1986
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.
Proceedings of the Proceedings International Test Conference 1986, 1986

1984
A New Timing Calibration Method for High Speed Memory Test.
Proceedings of the Proceedings International Test Conference 1984, 1984


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