Yasumasa Nishimura

According to our database, Yasumasa Nishimura authored at least 9 papers between 1984 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2004

Open architecture tester: what is a key issue of OAT?

Yasumasa Nishimura

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

1996

A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond.

Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami

IEEE J. Solid State Circuits, 1996

1993

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's.

Motomu Ukita, Shuji Murakami, Tadato Yamagata, Hirotada Kuriyama, Yasumasa Nishimura, Kenji Anami

IEEE J. Solid State Circuits, November, 1993

1991

A 21-mW 4-Mb CMOS SRAM for battery operation.

Shuji Murakami, Kore-aki Fujita, Motomu Ukita, Kazuhito Tsutsumi, Yasuo Inoue, Osamu Sakamoto, Motoi Ashida, Yasumasa Nishimura, Yoshio Kohno, Tadashi Nishimura, Kenji Anami

IEEE J. Solid State Circuits, November, 1991

An 8 ns 4 Mb serial access memory.

Hirotada Kuriyama, Toshihiko Hirose, Shuji Murakami, Tomohisa Wada, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami

IEEE J. Solid State Circuits, April, 1991

1990

A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture.

Toshihiko Hirose, Hirotada Kuriyama, Shuji Murakami, Kojiro Yuzuriha, Takao Mukai, Kazuhito Tsutsumi, Yasumasa Nishimura, Yoshio Kohno, Kenji Anami

IEEE J. Solid State Circuits, October, 1990

1989

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode.

Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima

IEEE J. Solid State Circuits, February, 1989

1986

Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.

Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka

Proceedings of the Proceedings International Test Conference 1986, 1986

1984

A New Timing Calibration Method for High Speed Memory Test.

Yasumasa Nishimura, Mitsuhiro Hamada, Y. Hayasaka

Proceedings of the Proceedings International Test Conference 1984, 1984