Yasuhiro Takahashi

Proceedings of the International Conference on Electronics, Information, and Communication, 2024

A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023

Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2023

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2023

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Divide-and-conquer verification method for noisy intermediate-scale quantum computation.

[BibT_eX]

[DOI]

Quantum, 2022

A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad.

[BibT_eX]

[DOI]

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2022

2021

Classically simulating quantum circuits with local depolarizing noise.

[BibT_eX]

[DOI]

Yuki Takeuchi

Theor. Comput. Sci., 2021

Power of uninitialized qubits in shallow quantum circuits.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2021

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices.

[BibT_eX]

[DOI]

Sensors, 2021

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function.

[BibT_eX]

[DOI]

SN Comput. Sci., 2020

Performance and Security Evaluation of S-Box Using Current-Pass Optimized Symmetric Pass Gate Adiabatic Logic.

[BibT_eX]

[DOI]

Hiroki Koyasu

SN Comput. Sci., 2020

Efficiently generating ground states is hard for postselected quantum computation.

[BibT_eX]

[DOI]

Yuki Takeuchi

CoRR, 2020

Message from the Technical Program Chairs iSES 2020.

[BibT_eX]

[DOI]

Tosiron Adegbija

Linga Reddy Cenkeramaddi

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

Special Session: An Adiabatic Logic Based Silicon Physical Unclonable Function.

[BibT_eX]

[DOI]

Kohei Ogura

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits.

[BibT_eX]

[DOI]

Hiroki Koyasu

IPSJ Trans. Syst. LSI Des. Methodol., 2019

Non-floating and low-power adiabatic logic circuit.

[BibT_eX]

[DOI]

Mei Han

IEICE Electron. Express, 2019

Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic Logic.

[BibT_eX]

[DOI]

Hiroki Koyasu

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor.

[BibT_eX]

[DOI]

Xiangyu Chen

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

5.3 GHz, 69.6 dBΩ Transimpedance Amplifier with Negative Impedance Converter.

[BibT_eX]

[DOI]

Ryo Tagawa

Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

A New Adiabatic Logic without Charge Sharing Gate for Cryptographic Devices.

[BibT_eX]

[DOI]

Ryosuke Ohashi

Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices.

[BibT_eX]

[DOI]

Apolinario Maria

Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

5.6 GHz, 61.7 dBΩ Transimpedance Amplifier Using Active Inductor in Shunt and Series Peaking Techniques.

[BibT_eX]

[DOI]

Takumi Fukuura

Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

2017

Operational amplifier based LC resonant circuit for adiabatic logic.

[BibT_eX]

[DOI]

Mei Han

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

Low power Adiabatic Logic based on 2PC2AL.

[BibT_eX]

[DOI]

Mei Han

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture.

[BibT_eX]

[DOI]

Yuya Kojima

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016

Commuting quantum circuits with few outputs are unlikely to be classically simulatable.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2016

Ancilla-driven instantaneous quantum polynomial time circuit for quantum supremacy.

[BibT_eX]

[DOI]

Yuki Takeuchi

CoRR, 2016

Shallow Quantum Circuits with Uninitialized Ancillary Qubits.

[BibT_eX]

[DOI]

CoRR, 2016

Collapse of the Hierarchy of Constant-Depth Exact Quantum Circuits.

[BibT_eX]

[DOI]

Comput. Complex., 2016

2015

Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2015

SPICE model of memristive device using Tukey window function.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

Two phase clocked subthreshold adiabatic logic circuit.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic.

[BibT_eX]

[DOI]

Rui Manuel de Oliveira Amaral Sarmento

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Power saving analysis of step-down buck converter using adiabatic switching principle.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

An improved estimation method of 4 port S-parameters with 2 port measurements.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

2014

Hardness of classically simulating quantum circuits with unbounded Toffoli and fan-out gates.

[BibT_eX]

[DOI]

Takeshi Yamazaki

Kazuyuki Tanaka

Quantum Inf. Comput., 2014

Process variation verification of low-power secure CSSAL AES S-box circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

An LSI implementation of a bit-parallel cellular multiplier over GF(2<sup>4</sup>) using secure charge-sharing symmetric adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Two phase clocking subthreshold adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Power dissipation analysis of memristor for low power integrated circuit applications.

[BibT_eX]

[DOI]

Haruki Ogata

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Dissemination of UTC(NICT) by Means of QZSS.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2013

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level.

[BibT_eX]

[DOI]

Microelectron. J., 2013

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 36th International Conference on Telecommunications and Signal Processing, 2013

DPA resistance of charge-sharing symmetric adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low power secure CSSAL bit-parallel multiplier over GF(2<sup>4</sup>) in 0.18μm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

An estimation method for the 3 port S-parameters with 1 port measurements.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier.

[BibT_eX]

[DOI]

Nazrul Anuar Nayan

Microelectron. J., 2012

Power-saving analysis of adiabatic logic in subthreshold region.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

A low-power sense amplifier for adiabatic memory using memristor.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2PCDAL: Two-phase clocking dual-rail adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Constant-Depth Exact Quantum Circuits for the OR and Threshold Functions

[BibT_eX]

[DOI]

CoRR, 2011

Multi Domain Test: Novel test strategy to reduce the Cost of Test.

[BibT_eX]

[DOI]

Akinori Maeda

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Actual implementation of multi domain test: Further reduction of cost of test.

[BibT_eX]

[DOI]

Akinori Maeda

Mitsuhiro Ogura

Proceedings of the 2011 IEEE International Test Conference, 2011

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

Low-power adiabatic SRAM.

[BibT_eX]

[DOI]

Hides Jamima

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

2010

Quantum addition circuits and unbounded fan-out.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2010

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Simple Sets of Measurements for Universal Quantum Computation and Graph State Preparation.

[BibT_eX]

[DOI]

Proceedings of the Theory of Quantum Computation, Communication, and Cryptography, 2010

2009

Quantum Arithmetic Circuits: A Survey.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Two phase clocked adiabatic static CMOS logic.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

A new horizontal and vertical common subexpression elimination method for multiple constant multiplication.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Fundamental logics based on two phase clocked adiabatic static CMOS logic.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

A fast quantum circuit for addition with few qubits.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2008

2007

The quantum fourier transform on a linear nearest neighbor architecture.

[BibT_eX]

[DOI]

Kazuo Ohta

Quantum Inf. Comput., 2007

VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2007

A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

A quantum circuit for shor's factoring algorithm using 2n + 2 qubits.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2006

2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

A linear-size quantum circuit for addition with no ancillary qubits.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2005

New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003

Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

On the computational power of constant-depth quantum circuits with gates for addition.

[BibT_eX]

[DOI]

Yasuhito Kawano

Masahiro Kitagawa

Proceedings of the IEEE Congress on Evolutionary Computation, 2003

2002

An efficient dialogue control method using decision tree-based estimation of out-of-vocabulary word attributes.

[BibT_eX]

[DOI]

Kohji Dohsaka

Kiyoaki Aikawa

Proceedings of the 7th International Conference on Spoken Language Processing, ICSLP2002, 2002

1992

B-ISDN Multimedia Communication and Collaboration Platform Using Advanced Video Workstations to Support Cooperative Work.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 1992

An integrated multimedia desktop communication and collaboration platform for broadband ISDN: the broadband ISDN group tele-working system.

[BibT_eX]

[DOI]

Tohru Hoshi