Yasuhiro Nakasha
According to our database1,
Yasuhiro Nakasha
authored at least 15 papers
between 1993 and 2024.
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Bibliography
2024
Sub-THz SC-FDE MIMO Systems with Deep Neural Network Equalization for 100 Gbps of 6G.
Proceedings of the 100th IEEE Vehicular Technology Conference, 2024
2023
High-Efficiency 250-320GHz Power Amplifiers Using InP-Based Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.
IEICE Trans. Electron., November, 2023
2022
First Demonstration of Crosstalk-Free (< -38.5 dB) 32-ch DWDM Demultiplexer on Standard Si PIC Platform.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022
2021
Demonstration of Crosstalk-Free WDM Demultiplexing on Si Nanowire PIC Controlled by Si CMOS ASIC.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021
Temperature-Tolerant Crosstalk-Free WDM Demultiplexing Using Controller-Integrated Cascaded AMZ Triplet (CAT) on Si Nano-Waveguide PIC Platform.
Proceedings of the European Conference on Optical Communication, 2021
2019
A Demultiplexer Immune from Fabrication-Error Impairments as an Enabler of Compact High-Channel-Count (> 64 ch) Dense WDM Systems on Low-End Si PIC Platforms.
Proceedings of the 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC), 2019
2017
2016
2015
Beyond 110 GHz InP-HEMT Based Mixer Module Using Flip-Chip Assembly for Precise Spectrum Analysis.
IEICE Trans. Electron., 2015
2013
Proceedings of the 2013 IEEE Radio and Wireless Symposium, 2013
2011
IEICE Trans. Electron., 2011
2007
A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology.
IEEE J. Solid State Circuits, 2007
2002
IEEE J. Solid State Circuits, 2002
1993
IEEE J. Solid State Circuits, September, 1993