Yasuhiro Nakakura

According to our database, Yasuhiro Nakakura authored at least 5 papers between 1989 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1998

An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting.

Takehiro Kamada, Toshihiko Fukuoka, Yuji Nakai, Yoshihiko Fukumoto, Yasuhiro Nakakura, Katsuhiko Ueda, Tomonori Shiomi, Kazuhiro Ota

J. VLSI Signal Process., 1998

1992

An Accurate, High Speed Implementation of Division by the Quasi-Unity Divisor Method.

Hiraku Nakano, Masaitsu Nakajima, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida

Proceedings of the Algorithms, Software, Architecture, 1992

1991

OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications.

Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

Parallel computer ADENART - its architecture and application.

Hiroshi Kadota, Katsuyuki Kaneko, Ichiro Okabayashi, Tadashi Okamoto, T. Mimura, Yasuhiro Nakakura, Akiyoshi Wakatani, Masaitsu Nakajima, Junji Nishikawa, K. Zaiki, Tatsuo Nogi

Proceedings of the 5th international conference on Supercomputing, 1991

1989

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit.

Katsuyuki Kaneko, Tadashi Okamoto, Masaitsu Nakajima, Yasuhiro Nakakura, Satoshi Gokita, Junji Nishikawa, Yuji Tanikawa, Hiroshi Kadota

IEEE J. Solid State Circuits, October, 1989