Yasuhiko Sasaki

According to our database, Yasuhiko Sasaki authored at least 6 papers between 1996 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2006

Constant-ratio-coupled multi-grain digital synchronizer with flexible input-output delay selection for versatility in low-power applications.

Yasuhiko Sasaki, Naoki Kato, Hiroaki Nakaya

IEEE J. Solid State Circuits, 2006

2003

Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology.

Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano

IEEE J. Solid State Circuits, 2003

2000

Multi-aggressor relative window method for timing analysis including crosstalk delay degradation.

Yasuhiko Sasaki, Kazuo Yano

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1998

Hole filling: a novel delay reduction technique using selector logic.

Shunzo Yamashita, Naoki Katoh, Yasuhiko Sasaki, Yohei Akita, Hidetoshi Chikata, Kazuo Yano

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis.

Yasuhiko Sasaki, Kunihito Rikino, Kazuo Yano

Proceedings of the ASP-DAC '98, 1998

1996

Top-down pass-transistor logic design.

Kazuo Yano, Yasuhiko Sasaki, Kunihito Rikino, Koichi Seki

IEEE J. Solid State Circuits, 1996