Yasuaki Nishitani
According to our database1,
Yasuaki Nishitani
authored at least 20 papers
between 1981 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
IEICE Trans. Inf. Syst., 2024
2023
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
2018
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
2014
Inf. Process. Lett., 2014
IEICE Trans. Inf. Syst., 2014
2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
2010
The Firing Squad Synchronization Problems for Number Patterns on a Seven-Segment Display and Segment Arrays.
IEICE Trans. Inf. Syst., 2010
2009
J. Circuits Syst. Comput., 2009
2006
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
1999
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999
1996
A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions.
Syst. Comput. Jpn., 1996
1995
Proceedings of the Algorithms and Computation, 6th International Symposium, 1995
1992
Syst. Comput. Jpn., 1992
1982
Theor. Comput. Sci., 1982
1981