Yasuaki Nishitani

According to our database, Yasuaki Nishitani authored at least 20 papers between 1981 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.

Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani

IEICE Trans. Inf. Syst., 2024

2023

Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.

Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

2018

Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units.

Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2016

New Two-Qubit Gate Library with Entanglement.

Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2014

The firing squad synchronization problem with sub-generals.

Kazuya Yamashita, Yasuaki Nishitani, Sadaki Hirose, Satoshi Okawa, Nobuyasu Osato

Inf. Process. Lett., 2014

A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.

Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani

IEICE Trans. Inf. Syst., 2014

2011

A Testable Realization for Decimal Multipliers.

Takashi Hirayama, Yasuaki Nishitani, Seiji Kitamura

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010

The Firing Squad Synchronization Problems for Number Patterns on a Seven-Segment Display and Segment Arrays.

Kazuya Yamashita, Mitsuru Sakai, Sadaki Hirose, Yasuaki Nishitani

IEICE Trans. Inf. Syst., 2010

2009

Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions.

Takashi Hirayama, Yasuaki Nishitani

J. Circuits Syst. Comput., 2009

2006

Efficient Search Methods for Obtaining Exact Minimum AND-EXOR Expressions.

Takashi Hirayama, Yasuaki Nishitani

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation.

Takashi Hirayama, Masatoshi Takahashi, Yasuaki Nishitani

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2002

A Faster Algorithm of Minimizing AND-EXOR Expressions.

Takashi Hirayama, Yasuaki Nishitani, Toru Sato

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

1999

Speedup of the n-Process Mutual Exclusion Algorithm.

Yoshihide Igarashi, Yasuaki Nishitani

Parallel Process. Lett., 1999

Speedup of Lockout-Free Mutual Exclusion Algorithms.

Yoshihide Igarashi, Yasuaki Nishitani

Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

1996

A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions.

Takashi Hirayama, Yasuaki Nishitani

Syst. Comput. Jpn., 1996

A Probably Optimal Embedding of Hyper-Rings in Hypercubes.

Koji Obokata, Yasuaki Nishitani, Yoshihide Igarashi

Inf. Process. Lett., 1996

1995

Embeddings of Hyper-Rings in Hypercubes.

Yukihiro Hamada, Aohan Mei, Yasuaki Nishitani, Yoshihide Igarashi

Proceedings of the Algorithms and Computation, 6th International Symposium, 1995

1992

Graph representation of logic functions to design two-level MOS networks.

Yasuaki Nishitani, Kensuke Shimizu, Masahiko Nagumo

Syst. Comput. Jpn., 1992

1982

On Universality of Concurrent Expressions with Synchronization Primitives.

T. Ito, Yasuaki Nishitani

Theor. Comput. Sci., 1982

1981

The Firing Squad Synchronization Problem for Graphs.

Yasuaki Nishitani, Namio Honda

Theor. Comput. Sci., 1981