Yasser Sherazi

According to our database, Yasser Sherazi authored at least 5 papers between 2015 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

A Novel Design Reversible Logic Based Configurable Fault-Tolerant Embryonic Hardware.

Kasem Khalil, Bappaditya Dey, Yasser Sherazi, Ashok Kumar, Magdy A. Bayoumi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2017

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.

Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options.

Luca Mattii, Dragomir Milojevic, Peter Debacker, Yasser Sherazi, Mladen Berekovic, Praveen Raghavan

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2015

Area and routing efficiency of SWD circuits compared to advanced CMOS.

Odysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubotaru, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Aaron Thean

Proceedings of the 2015 International Conference on IC Design & Technology, 2015