Yasong Cao

Orcid: 0009-0003-7683-989X

According to our database1, Yasong Cao authored at least 8 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024

BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms GEMM.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2022
TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Mentha: Enabling Sparse-Packing Computation on Systolic Arrays.
Proceedings of the 51st International Conference on Parallel Processing, 2022

BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications.
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022

2021
Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators.
Proceedings of the 2021 IEEE 23rd Int Conf on High Performance Computing & Communications; 7th Int Conf on Data Science & Systems; 19th Int Conf on Smart City; 7th Int Conf on Dependability in Sensor, 2021


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