Yashwant K. Malaiya

Orcid: 0000-0002-1825-1671

Affiliations:
  • Colorado State University, USA


According to our database1, Yashwant K. Malaiya authored at least 97 papers between 1978 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Bibliography

2023
Comparison of Agile Scaling Frameworks.
Proceedings of the 2023 6th International Conference on Information Science and Systems, 2023

2021
Social media analytics of the Internet of Things.
Discov. Internet Things, 2021

2020
Adaptive Testing Based on Moment Estimation.
IEEE Trans. Syst. Man Cybern. Syst., 2020

2019
Quality Model for Testing Augmented Reality Applications.
Proceedings of the 10th IEEE Annual Ubiquitous Computing, 2019

An API Development Model for Digital Twins.
Proceedings of the 19th IEEE International Conference on Software Quality, 2019

2017
Periodicity in software vulnerability discovery, patching and exploitation.
Int. J. Inf. Sec., 2017

2016
Assessing vulnerability exploitability risk using software properties.
Softw. Qual. J., 2016

Evaluating CVSS Base Score Using Vulnerability Rewards Programs.
Proceedings of the ICT Systems Security and Privacy Protection, 2016

To Fear or Not to Fear That is the Question: Code Characteristics of a Vulnerable Functionwith an Existing Exploit.
Proceedings of the Sixth ACM on Conference on Data and Application Security and Privacy, 2016

2015
Comparing and Evaluating CVSS Base Metrics and Microsoft Rating System.
Proceedings of the 2015 IEEE International Conference on Software Quality, 2015

2014
Modeling Skewness in Vulnerability Discovery.
Qual. Reliab. Eng. Int., 2014

Using Software Structure to Predict Vulnerability Exploitation Potential.
Proceedings of the IEEE Eighth International Conference on Software Security and Reliability, 2014

Are the Classical Disaster Recovery Tiers Still Applicable Today?
Proceedings of the 25th IEEE International Symposium on Software Reliability Engineering Workshops, 2014

Using Attack Surface Entry Points and Reachability Analysis to Assess the Risk of Software Vulnerability Exploitability.
Proceedings of the 15th International IEEE Symposium on High-Assurance Systems Engineering, 2014

2012
Assessing Disaster Recovery Alternatives: On-Site, Colocation or Cloud.
Proceedings of the 23rd IEEE International Symposium on Software Reliability Engineering Workshops, 2012

2011
Modeling vulnerability discovery process in Apache and IIS HTTP servers.
Comput. Secur., 2011

2010
Principal Component Analysis-based compensation for measurement errors due to mechanical misalignments in PCB testing.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
An outlier detection based approach for PCB testing.
Proceedings of the 2009 IEEE International Test Conference, 2009

Seasonal Variation in the Vulnerability Discovery Process.
Proceedings of the Second International Conference on Software Testing Verification and Validation, 2009

2008
Antirandom Testing: A Distance-Based Approach.
VLSI Design, 2008

Application of Vulnerability Discovery Models to Major Operating Systems.
IEEE Trans. Reliab., 2008

Seasonality in Vulnerability Discovery in Major Software Systems.
Proceedings of the 19th International Symposium on Software Reliability Engineering (ISSRE 2008), 2008

Vulnerability Discovery Modeling Using Weibull Distribution.
Proceedings of the 19th International Symposium on Software Reliability Engineering (ISSRE 2008), 2008

2007
Measuring, analyzing and predicting security vulnerabilities in software systems.
Comput. Secur., 2007

Vulnerability Discovery in Multi-Version Software Systems.
Proceedings of the Tenth IEEE International Symposium on High Assurance Systems Engineering (HASE 2007), 2007

2006
X-IDDQ: A Novel Defect Detection Technique Using IDDQ Data.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Measuring and Enhancing Prediction Capabilities of Vulnerability Discovery Models for Apache and IIS HTTP Servers.
Proceedings of the 17th International Symposium on Software Reliability Engineering (ISSRE 2006), 2006

Assessing Vulnerabilities in Apache and IIS HTTP Servers.
Proceedings of the Second International Symposium on Dependable Autonomic and Secure Computing (DASC 2006), 29 September, 2006

Security vulnerability categories in major software systems.
Proceedings of the Third IASTED International Conference on Communication, 2006

2005
Modeling the Vulnerability Discovery Process.
Proceedings of the 16th International Symposium on Software Reliability Engineering (ISSRE 2005), 2005

Security Vulnerabilities in Software Systems: A Quantitative Perspective.
Proceedings of the Data and Applications Security XIX, 2005

Dynamic power minimization during combinational circuit testing as a traveling salesman problem.
Proceedings of the IEEE Congress on Evolutionary Computation, 2005

2004
Augmenting Test Case Generation Using Statechart.
Proceedings of the International Conference on Software Engineering Research and Practice, 2004

2002
Software reliability growth with test coverage.
IEEE Trans. Reliab., 2002

2000
Module Size Distribution and Defect Density.
Proceedings of the 11th International Symposium on Software Reliability Engineering (ISSRE 2000), 2000

1999
Requirements volatility and defect density.
Proceedings of the 10th International Symposium on Software Reliability Engineering, 1999

1998
Antirandom vs. pseudorandom testing.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Estimating the Number of Residual Defects.
Proceedings of the 3rd IEEE International Symposium on High-Assurance Systems Engineering (HASE '98), 1998

1997
Operational and Test Performance in the Presence of Built-in Current Sensors.
VLSI Design, 1997

Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I<sub>DDQ</sub> Testing in BiCMOS and CMOS Circuits.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Automatic test generation using checkpoint encoding and antirandom testing.
Proceedings of the Eighth International Symposium on Software Reliability Engineering, 1997

What do the software reliability growth model parameters represent?
Proceedings of the Eighth International Symposium on Software Reliability Engineering, 1997

1996
Fault Modeling of ECL for High Fault Coverage of Physical Defects.
VLSI Design, 1996

Fault exposure ratio estimation and applications.
Proceedings of the Seventh International Symposium on Software Reliability Engineering, 1996

Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995
Testable design of BiCMOS circuits for stuck-open fault detection using single patterns.
IEEE J. Solid State Circuits, August, 1995

Interconnection of FDDI-II networks through an ATM backbone - An analysis.
Proceedings of the Proceedings 20th Conference on Local Computer Networks (LCN'95), 1995

Antirandom testing: getting the most out of black-box testing.
Proceedings of the Sixth International Symposium on Software Reliability Engineering, 1995

ROBUST: a next generation software reliability engineering tool.
Proceedings of the Sixth International Symposium on Software Reliability Engineering, 1995

A Novel High-Speed BiCMOS Domino Logic Family.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Resolution Enhancement in I<sub>DDQ</sub> Testing for Large ICs.
VLSI Design, 1994

Input pattern classification for transistor level testing of BiCMOS circuits.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

The Effect of Built-In Current Sensors (BICS) on Operational and Test Performance.
Proceedings of the Seventh International Conference on VLSI Design, 1994

The relationship between test coverage and reliability.
Proceedings of the 5th International Symposium on Software Reliability Engineering, 1994

On input profile selection for software testing.
Proceedings of the 5th International Symposium on Software Reliability Engineering, 1994

1993
Faulty behavior of storage elements and its effects on sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1993

An Examination of Fault Exposure Ratio.
IEEE Trans. Software Eng., 1993

Testable design for BiCMOS stuck-open fault detection.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Use of Storage Elements as Primitives for Modelling Faults in Synchronous Sequential Circuits.
Proceedings of the Sixth International Conference on VLSI Design, 1993

The effect of correlated faults on software reliability.
Proceedings of the Fourth International Symposium on Software Reliability Engineering, 1993

On the need for simulation for better characterization of software reliability.
Proceedings of the Fourth International Symposium on Software Reliability Engineering, 1993

Enhancing accuracy of software reliability prediction.
Proceedings of the Fourth International Symposium on Software Reliability Engineering, 1993

Test Generation for BiCMOS Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
Prediction of Software Reliability Using Connectionist Models.
IEEE Trans. Software Eng., 1992

Steps to Practical Reliability Meassurement - Guest Editors' Introduction.
IEEE Softw., 1992

Using Neural Networks in Reliability Prediction.
IEEE Softw., 1992

Guest Editor's Introduction: VLSI Design 92.
IEEE Des. Test Comput., 1992

Behavior of faulty single BJT BiCMOS logic gates.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

On Bridging Faults in ECL Circuits.
Proceedings of the Fifth International Conference on VLSI Design, 1992

The nature of fault exposure ratio.
Proceedings of the Third International Symposium on Software Reliability Engineering, 1992

The scaling problem in neural networks for software reliability prediction.
Proceedings of the Third International Symposium on Software Reliability Engineering, 1992

1991
Analysis of Detection Capability of Parallel Signature Analyzers.
IEEE Trans. Computers, 1991

An analysis and testing of operation induced faults in MOS VLSI.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Enhancement of resolution in supply current based testing for large ICs.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Evaluation of detectability in BIST environment.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Prediction of software reliability using neural networks.
Proceedings of the Second International Symposium on Software Reliability Engineering, 1991

Gate level representation of ECL circuits for fault modeling.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

An Introduction to Software Reliability Models.
Proceedings of the 17th International Computer Measurement Group Conference, 1991

1990
On the testing of microprogrammed processor.
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

Predictability measures for software reliability models.
Proceedings of the Fourteenth Annual International Computer Software and Applications Conference, 1990

1989
CMOS open-fault detection in the presence of glitches and timing skews.
IEEE J. Solid State Circuits, August, 1989

CMOS stuck-open fault testability.
IEEE J. Solid State Circuits, February, 1989

Limitations of switch level analysis for bridging faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

On inherent untestability of unaugmented microprogrammed control.
Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989

CMOS Stuck-open Fault Detection Using Single Test Patterns.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Design of a testable RISC-to-CISC control architecture.
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

1987
On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1985
Faults in Microprogrammed and Hardwired Control.
Proceedings of the Proceedings International Test Conference 1985, 1985

1984
Modeling and Testing for Timing Faults in Synchronous Sequential Circuits.
IEEE Des. Test, 1984

The Coverage Problem for Random Testing.
Proceedings of the Proceedings International Test Conference 1984, 1984

1983
Testing for Timing Faults in Synchronous Sequential Integrated Circuits.
Proceedings of the Proceedings International Test Conference 1983, 1983

1982
A New Fault Model and Testing Technique for CMOS Devices.
Proceedings of the Proceedings International Test Conference 1982, 1982

1981
Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults.
IEEE Trans. Computers, 1981

Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits.
IEEE Trans. Computers, 1981

State Diagram Approach for Functional Testing of Control Section.
Proceedings of the Proceedings International Test Conference 1981, 1981

1979
A survey of methods for intermittent fault analysis.
Proceedings of the 1979 International Workshop on Managing Requirements Knowledge, 1979

1978
A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults.
IEEE Trans. Computers, 1978


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