Yaseer Arafat Durrani

According to our database, Yaseer Arafat Durrani authored at least 14 papers between 2006 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Efficient power macromodeling approach for an IP-based SoC system using discrete water cycle algorithm.

Faisal Siddiq, Yaseer Arafat Durrani

Turkish J. Electr. Eng. Comput. Sci., May, 2021

2018

Power Analysis Approach for NoC-based Homogeneous Stacked 3D ICs.

Yaseer Arafat Durrani

J. Circuits Syst. Comput., 2018

2016

Efficient power analysis approach and its application to system-on-chip design.

Yaseer Arafat Durrani, Teresa Riesgo

Microprocess. Microsystems, 2016

2014

Power estimation for intellectual property-based digital systems at the architectural level.

Yaseer Arafat Durrani, Teresa Riesgo

J. King Saud Univ. Comput. Inf. Sci., 2014

High-Level Power Analysis for Intellectual Property-Based Digital Systems.

Yaseer Arafat Durrani, Teresa Riesgo

Circuits Syst. Signal Process., 2014

2011

Efficient power macromodeling technique for conventional MOS transistors.

Yaseer Arafat Durrani

Proceedings of the International Conference on Electrical Engineering and Informatics, 2011

2009

Power estimation technique for DSP architectures.

Yaseer Arafat Durrani, Teresa Riesgo

Digit. Signal Process., 2009

2007

Architectural Power Analysis for Intellectual Property-Based Digital System.

Yaseer Arafat Durrani, Teresa Riesgo

J. Low Power Electron., 2007

Efficient Power Macromodeling Technique for IP-Based Digital System.

Yaseer Arafat Durrani, Ana Abril, Teresa Riesgo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

LUT-Based Power Macromodeling Technique for DSP Architectures.

Yaseer Arafat Durrani, Teresa Riesgo

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Power Macromodeling for High Level Power Estimation.

Yaseer Arafat Durrani, Teresa Riesgo

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Power Estimation for IP-Based Modules.

Yaseer Arafat Durrani, Teresa Riesgo

Proceedings of the International Symposium on System-on-Chip, 2006

Power estimation for register transfer level by genetic algorithm.

Yaseer Arafat Durrani, Teresa Riesgo, Felipe Machado

Proceedings of the ICINCO 2006, 2006

Power Macromodeling for IP Modules.

Yaseer Arafat Durrani, Teresa Riesgo

Proceedings of the 13th IEEE International Conference on Electronics, 2006