Yarsun Hsu
According to our database1,
Yarsun Hsu
authored at least 55 papers
between 1989 and 2016.
Collaborative distances:
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Bibliography
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
DeAr: A framework for power-efficient and flexible embedded digital signal processor design.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Message scheduling and timing analysis for flexray dynamic segment by considering slot-multiplexing.
Proceedings of the IEEE International Conference on Vehicular Electronics and Safety, 2015
2014
Design and Evaluation of Dynamically-Allocated Multi-queue Buffers with Multiple Packets for NoC Routers.
Proceedings of the Sixth International Symposium on Parallel Architectures, 2014
Proceedings of the Sixth International Symposium on Parallel Architectures, 2014
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014
Proceedings of the Algorithms and Architectures for Parallel Processing, 2014
2013
Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2013
2012
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking.
J. Signal Process. Syst., 2012
A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 2012 International Conference on Connected Vehicles and Expo, 2012
2011
Implementation and analysis of speculative flow control for on-chip interconnection network.
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011
A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010
2009
Proceedings of the 2009 Workshop on Embedded Systems Education, 2009
2008
A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications, 2008
2007
IEICE Trans. Inf. Syst., 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the High Performance Computing and Communications, 2007
Proceedings of the High Performance Computing and Communications, 2007
2006
Proceedings of the High Performance Computing and Communications, 2006
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006
2005
A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2000
Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 2000
1997
Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997
1996
Proceedings of the Input/Output in Parallel and Distributed Computer Systems., 1996
Proceedings of the Input/Output in Parallel and Distributed Computer Systems., 1996
Proceedings of the Input/Output in Parallel and Distributed Computer Systems., 1996
1995
IEEE Trans. Computers, 1995
IEEE Parallel Distributed Technol. Syst. Appl., 1995
Proceedings of IPPS '95, 1995
Proceedings of the 9th international conference on Supercomputing, 1995
1994
SIGARCH Comput. Archit. News, 1994
Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994
1993
IEEE Trans. Computers, 1993
Proceedings of the 1993 International Conference on Parallel Processing, 1993
1992
Proceedings of the Sixteenth Annual International Computer Software and Applications Conference, 1992
1991
The Effects of Network Delays on the Performance of MIN-Based Cache Coherence Protocols.
Proceedings of the International Conference on Parallel Processing, 1991
1990
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
Proceedings of the CONPAR 90, 1990
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989