Yaoyu Tao

According to our database, Yaoyu Tao authored at least 20 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.

Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang

IEEE J. Solid State Circuits, April, 2024

MeMCISA: Memristor-Enabled Memory-Centric Instruction-Set Architecture for Database Workloads.

Yihang Zhu, Lei Cai, Lianfeng Yu, Anjunyi Fan, Longhao Yan, Zhaokun Jing, Bonan Yan, Pek Jun Tiw, Yuqi Li, Yaoyu Tao, Yuchao Yang

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

2023

Hadamard product-based in-memory computing design for floating point neural network training.

Anjunyi Fan, Yihan Fu, Yaoyu Tao, Zhonghua Jin, Haiyue Han, Huiyu Liu, Yaojun Zhang, Bonan Yan, Yuchao Yang, Ru Huang

Neuromorph. Comput. Eng., March, 2023

Fast and reconfigurable sort-in-memory system enabled by memristors.

Lianfeng Yu, Yaoyu Tao, Teng Zhang, Zeyu Wang, Xile Wang, Zelun Pan, Bowen Wang, Zhaokun Jing, Jiaxin Liu, Yuqi Li, Yihang Zhu, Bonan Yan, Yuchao Yang

CoRR, 2023

Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm² AIB 2.0 Interface to Provide Versatile Workload Acceleration.

Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs.

Junkang Zhu, Yaoyu Tao, Zhengya Zhang

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search.

Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao, Yuchao Yang

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022

Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm.

Lianfeng Yu, Zhaokun Jing, Yuchao Yang, Yaoyu Tao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder.

Yaoyu Tao, Cedric Choi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture.

Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang

IEEE J. Solid State Circuits, 2021

HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer.

Yaoyu Tao, Zhengya Zhang

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

DNC-Aided SCL-Flip Decoding of Polar Codes.

Yaoyu Tao, Zhengya Zhang

Proceedings of the IEEE Global Communications Conference, 2021

2019

Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes.

Yaoyu Tao, Shuanghong Sun, Zhengya Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 3.25Gb/s, 13.2pJ/b, 0.64mm² Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS.

Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

An Automated FPGA-Based Framework for Rapid Prototyping of Nonbinary LDPC Codes.

Yaoyu Tao, Qi Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2015

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating.

Youn Sung Park, Yaoyu Tao, Zhengya Zhang

IEEE J. Solid State Circuits, 2015

2014

A 4.68Gb/s belief propagation polar decoder with bit-splitting register file.

Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang

Proceedings of the Symposium on VLSI Circuits, 2014

2013

A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating.

Youn Sung Park, Yaoyu Tao, Zhengya Zhang

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Efficient in situ error detection enabling diverse path coverage.

Chia-Hsiang Chen, Yaoyu Tao, Zhengya Zhang

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders.

Yaoyu Tao, Youn Sung Park, Zhengya Zhang

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012