Yaolei Li
Orcid: 0000-0002-6640-1275
According to our database1,
Yaolei Li
authored at least 6 papers
between 2023 and 2024.
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Bibliography
2024
RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
34.7 A 28nm 2.4Mb/mm<sup>2</sup> 6.9 - 16.3TOPS/mm<sup>2</sup> eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023