Yao Xin

Orcid: 0000-0002-6495-081X

According to our database1, Yao Xin authored at least 24 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Recursive Multi-Tree Construction With Efficient Rule Sifting for Packet Classification on FPGA.
IEEE/ACM Trans. Netw., April, 2024

A novel low-latency scheduling approach of TSN for multi-link rate networking.
Comput. Networks, 2024

Bubble Sketch: A High-performance and Memory-efficient Sketch for Finding Top-<i>k</i> Items in Data Streams.
Proceedings of the 33rd ACM International Conference on Information and Knowledge Management, 2024

2023
A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets.
IEEE Micro, 2023

MCCQF: Low-Latency Transmission Based on IEEE 802.1 Qch For Hierarchical Networking.
Proceedings of the IEEE International Conference on Communications, 2023

Building a High-Performance Data Channel for the Federal Cyber Range.
Proceedings of the 8th International Conference on Data Science in Cyberspace, 2023

Comparative analysis of neural networks techniques to forecast Airfare Prices.
Proceedings of the 47th IEEE Annual Computers, Software, and Applications Conference, 2023

2022
FPGA-Based Updatable Packet Classification Using TSS-Combined Bit-Selecting Tree.
IEEE/ACM Trans. Netw., 2022

High Throughput Hardware/Software Heterogeneous System for RRPN-Based Scene Text Detection.
IEEE Trans. Computers, 2022

A Versatility-Performance Balanced Hardware Architecture for Scene Text Detection.
Proceedings of the IEEE Smartworld, 2022

Updatable Packet Classification on FPGA with Bounded Worst-Case Performance.
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2022

HybridTSS: A Recursive Scheme Combining Coarse- and Fine- Grained Tuples for Packet Classification.
Proceedings of the 6th Asia-Pacific Workshop on Networking, 2022

2021
An FPGA-based High-Throughput Packet Classification Architecture Supporting Dynamic Updates for Large-Scale Rule Sets.
Proceedings of the 2021 IEEE Conference on Computer Communications Workshops, 2021

KickTree: A Recursive Algorithmic Scheme for Packet Classification with Bounded Worst-Case Performance.
Proceedings of the ANCS '21: Symposium on Architectures for Networking and Communications Systems, Layfette, IN, USA, December 13, 2021

2016
An FPGA-Based High-Performance Neural Ensemble Spiking Activity Simulator Utilizing Generalized Volterra Kernel and Complexity Analysis.
J. Circuits Syst. Comput., 2016

FPGA-Based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery.
Frontiers Robotics AI, 2016

2015
An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics.
IEEE ACM Trans. Comput. Biol. Bioinform., 2015

2014
An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking.
Microelectron. J., 2014

GPU-based biclustering for microarray data analysis in neurocomputing.
Neurocomputing, 2014

VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernel.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Laguerre-volterra model and architecture for MIMO system identification and output prediction.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

2013
Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform.
Microelectron. J., 2013

Erratum to "Finding the most efficient DMUs in DEA: An improved integrated model" [Comput. Indus. Eng. 52 (2007) 71-77].
Comput. Ind. Eng., 2013

A customizable Stochastic State Point Process Filter (SSPPF) for neural spiking activity.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013


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