Yao Wang

According to our database, Yao Wang authored at least 7 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Secure Dynamic Memory Scheduling Against Timing Channel Attacks.

Yao Wang, Benjamin Wu, G. Edward Suh

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016

Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller.

Andrew Ferraiuolo, Yao Wang, Danfeng Zhang, Andrew C. Myers, G. Edward Suh

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

SecDCP: secure dynamic cache partitioning for efficient timing channel protection.

Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, G. Edward Suh

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

A Hardware Design Language for Timing-Sensitive Information-Flow Security.

Danfeng Zhang, Yao Wang, G. Edward Suh, Andrew C. Myers

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Timing channel protection for a shared memory controller.

Yao Wang, Andrew Ferraiuolo, G. Edward Suh

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Quadrisection-based task mapping on many-core processors for energy-efficient on-chip communication.

Nithin Michael, Yao Wang, G. Edward Suh, Ao Tang

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

2012

Efficient Timing Channel Protection for On-Chip Networks.

Yao Wang, G. Edward Suh

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012