Yao-Chia Liu

According to our database, Yao-Chia Liu authored at least 4 papers between 2013 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 36-Gb/s 1.6-pJ/b PAM-3 Transmitter Leveraging Digital Logic Cells and 4-Tap FFE in 22-nm CMOS.

Philex Ming-Yan Fan, Ming-Xun Wang, Wei-Ting Lin, Yao-Chia Liu

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2025

2023

A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement.

Yao-Chia Liu, Wei-Zen Chen, Yuan-Sheng Lee, Yu-Hsiang Chen, Shawn Ming, Ying-Hsi Lin

IEEE J. Solid State Circuits, October, 2023

2015

A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery.

Zheng-Hao Hong, Yao-Chia Liu, Wei-Zen Chen

IEEE J. Solid State Circuits, 2015

2013

A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector.

Yao-Chia Liu, Wei-Zen Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Yen-Wei Lee, Min-Shueh Yuan

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013