Yao-Chang Yang
According to our database1,
Yao-Chang Yang
authored at least 10 papers
between 2006 and 2011.
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Bibliography
2011
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Low complexity fractional motion estimation with adaptive mode selection for H.264/AVC.
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010
2009
IEEE Trans. Circuits Syst. Video Technol., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2007
IEEE J. Solid State Circuits, 2007
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006
A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006