Yanyue Xie
Orcid: 0000-0002-4325-521X
According to our database1,
Yanyue Xie
authored at least 21 papers
between 2020 and 2024.
Collaborative distances:
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Bibliography
2024
MoE-Pruner: Pruning Mixture-of-Experts Large Language Model using the Hints from Its Router.
CoRR, 2024
HybridFlow: Infusing Continuity into Masked Codebook for Extreme Low-Bitrate Image Compression.
Proceedings of the 32nd ACM International Conference on Multimedia, MM 2024, Melbourne, VIC, Australia, 28 October 2024, 2024
Quasar-ViT: Hardware-Oriented Quantization-Aware Architecture Search for Vision Transformers.
Proceedings of the 38th ACM International Conference on Supercomputing, 2024
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024
SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum- Flux - Parametron Superconducting Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
A Life-Cycle Energy and Inventory Analysis of Adiabatic Quantum-Flux-Parametron Circuits.
CoRR, 2023
SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Peeling the Onion: Hierarchical Reduction of Data Redundancy for Efficient Vision Transformer Training.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
You Already Have It: A Generator-Free Low-Precision DNN Training Framework Using Stochastic Rounding.
Proceedings of the Computer Vision - ECCV 2022, 2022
FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Hardware-efficient stochastic rounding unit design for DNN training: late breaking results.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs<sup>*</sup>.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020