Yanqing Zhang

Affiliations:
  • NVIDIA Inc., Santa Clara, CA, USA
  • University of Virginia, Charlottesville, VA, USA (PhD)


According to our database1, Yanqing Zhang authored at least 31 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2024
BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Machine Learning and Algorithms: Let Us Team Up for EDA.
IEEE Des. Test, February, 2023

GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus.
Proceedings of the 51st International Conference on Parallel Processing, 2022

Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper).
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

GATSPI: GPU accelerated gate-level simulation for power improvement.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Simba: scaling deep-learning inference with chiplet-based architecture.
Commun. ACM, 2021

2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Accelerating Chip Design With Machine Learning.
IEEE Micro, 2020

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.
IEEE J. Solid State Circuits, 2020

MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification.
CoRR, 2020

Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

MAGNet: A Modular Accelerator Generator for Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

PRIMAL: Power Inference using Machine Learning.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

2015
21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Fast, accurate variation-aware path timing computation for sub-threshold circuits.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
A Batteryless 19 µW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications.
IEEE J. Solid State Circuits, 2013

2012
A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Body Sensor Networks: A Holistic Approach From Silicon to Users.
Proc. IEEE, 2012

A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A custom processor for node and power management of a battery-less body sensor node in 130nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010
System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


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