Yannick Bonhomme

According to our database, Yannick Bonhomme authored at least 20 papers between 2001 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Memory Reliability Improvement Based on Maximized Error-Correcting Codes.

Valentin Gherman, Samuel Evain, Yannick Bonhomme

J. Electron. Test., 2013

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.

Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Memory reliability improvements based on maximized error-correcting codes.

Valentin Gherman, Samuel Evain, Yannick Bonhomme

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Programmable extended SEC-DED codes for memory errors.

Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Generalized parity-check matrices for SEC-DED codes with fixed parity.

Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Error prediction based on concurrent self-test and reduced slack time.

Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Programmable restricted SEC codes to mask permanent faults in semiconductor memories.

Samuel Evain, Yannick Bonhomme, Valentin Gherman

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009

Transaction-based modeling for large scale simulations of heterogeneous systems.

Richard Buchmann, Mickael Cartron, Yannick Bonhomme

Proceedings of the 2nd International Conference on Simulation Tools and Techniques for Communications, 2009

System-level hardware-based protection of memories against soft-errors.

Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Power-On Controller for high lifetime wireless sensor nodes.

Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme

Proceedings of the Wireless Sensor and Actor Networks II, 2008

2006

A Gated Clock Scheme for Low Power Testing of Logic Cores.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

J. Electron. Test., 2006

2005

Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.

Patrick Girard, Yannick Bonhomme

J. Low Power Electron., 2005

2004

Power-Driven Routing-Constrained Scan Chain Design.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

J. Electron. Test., 2004

An efficient scan tree design for test time reduction.

Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard

Proceedings of the 9th European Test Symposium, 2004

Design of Routing-Constrained Low Power Scan Chains.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Power Driven Chaining of Flip-Flops in Scan Architectures.

Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Power: a Big Issue in Large SOC Designs.

Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

A Gated Clock Scheme for Low Power Scan-Based BIST.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001