Yannan Nellie Wu

According to our database, Yannan Nellie Wu authored at least 10 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space.

Michael Gilbert, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze

CoRR, 2024

2023

Systematic Modeling and Design of Sparse Deep Neural Network Accelerators

Yannan Nellie Wu

PhD thesis, 2023

Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity.

Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity.

Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators.

Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2022

Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling.

Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021

Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators.

Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Architecture-Level Energy Estimation for Heterogeneous Computing Systems.

Francis Wang, Yannan Nellie Wu, Matthew E. Woicik, Joel S. Emer, Vivienne Sze

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

2020

An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs.

Yannan Nellie Wu, Vivienne Sze, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019

Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs.

Yannan Nellie Wu, Joel S. Emer, Vivienne Sze

Proceedings of the International Conference on Computer-Aided Design, 2019