Yann Delomier

According to our database1, Yann Delomier authored at least 8 papers between 2016 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2020
Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices.
J. Signal Process. Syst., 2020

Model-based Design of Hardware SC Polar Decoders for FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2020

Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

2019
Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

2018
Model-based Design of Efficient LDPC Decoder Architectures.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

From multicore LDPC decoder implementations to FPGA decoder architectures: a case study.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2016
Implementation and simulation of the impact of mixer phase mismatch in cartesian feedback linearization systems.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016


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