Yang Yang

Affiliations:
  • University of Southern California, Department of Electrical and Computer Engineering, Los Angeles, CA, USA
  • University of California, Riverside, CA, USA


According to our database1, Yang Yang authored at least 14 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Bandwidth Efficient Homomorphic Encrypted Discrete Fourier Transform Acceleration on FPGA.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

A Framework for Generating Accelerators for Homomorphic Encryption Operations on FPGAs.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023
FPGA Acceleration of Rotation in Homomorphic Encryption Using Dynamic Data Layout.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022
Bandwidth Efficient Homomorphic Encrypted Matrix Vector Multiplication Accelerator on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2022

FPGA Accelerator for Homomorphic Encrypted Sparse Convolutional Neural Network Inference.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

NTTGen: a framework for generating low latency NTT implementations on FPGA.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2021
FPGA Acceleration of Number Theoretic Transform.
Proceedings of the High Performance Computing - 36th International Conference, 2021

2020
FASTHash: FPGA-Based High Throughput Parallel Hash Table.
Proceedings of the High Performance Computing - 35th International Conference, 2020

A High Throughput Parallel Hash Table Accelerator on HBM-enabled FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2020

A High Throughput Parallel Hash Table on FPGA using XOR-based Memory.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

How to Efficiently Train Your AI Agent? Characterizing and Evaluating Deep Reinforcement Learning on Heterogeneous Platforms.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2019
Parallel Totally Induced Edge Sampling on FPGAs.
Proceedings of the Parallel Computing: Technology Trends, 2019

2013
Shared memory heterogeneous computation on PCIe-supported platforms.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
An efficient dynamic multiple-candidate motion vector approach for GPU-based hierarchical motion estimation.
Proceedings of the 31st IEEE International Performance Computing and Communications Conference, 2012


  Loading...