Yang Yang

According to our database, Yang Yang authored at least 13 papers between 2004 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2015

Efficient distribution of Triggered Synchronous Block Diagrams on asynchronous platforms.

Yang Yang, Stavros Tripakis, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

2012

Software Synthesis for Distributed Embedded Systems.

Yang Yang

PhD thesis, 2012

Development of Building Automation and Control Systems.

Yang Yang, Qi Zhu, Mehdi Maasoumy, Alberto L. Sangiovanni-Vincentelli

IEEE Des. Test Comput., 2012

2010

Optimizing the Software Architecture for Extensibility in Hard Real-time Distributed Systems.

Qi Zhu, Yang Yang, Marco Di Natale, Eelco Scholte, Alberto L. Sangiovanni-Vincentelli

IEEE Trans. Ind. Informatics, 2010

A Design Flow for Building Automation and Control Systems.

Yang Yang, Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli, Qi Zhu

Proceedings of the 31st IEEE Real-Time Systems Symposium, 2010

2009

Optimizing Extensibility in Hard Real-Time Distributed Systems.

Qi Zhu, Yang Yang, Eelco Scholte, Marco Di Natale, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 15th IEEE Real-Time and Embedded Technology and Applications Symposium, 2009

2006

Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design.

Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang

IEEE Trans. Circuits Syst. II Express Briefs, 2006

2005

Spanning graph-based nonrectilinear steiner tree algorithms.

Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design.

Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

The polygonal contraction heuristic for rectilinear Steiner tree construction.

Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.

Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design.

Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan

Proceedings of the Integrated Circuit and System Design, 2004

Efficient octilinear Steiner tree construction based on spanning graphs.

Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004