Yang Sun
Affiliations:- Rice University, Department of Electrical and Computer Engineering, Houston, TX, USA (PhD 2010)
According to our database1,
Yang Sun
authored at least 27 papers
between 2007 and 2014.
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Bibliography
2014
Parallel Interleaver Design for a High Throughput HSPA+/LTE Multi-Standard Turbo Decoder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
2012
High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture.
IEEE Trans. Signal Process., 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
J. Signal Process. Syst., 2011
J. Signal Process. Syst., 2011
Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder.
Integr., 2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
Low-complexity and high-performance soft MIMO detection based on distributed M-algorithm through trellis-diagram.
Proceedings of the IEEE International Conference on Acoustics, 2010
Proceedings of the 5th International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
2007
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007