Yang-Lo Ahn
According to our database1,
Yang-Lo Ahn
authored at least 6 papers
between 2012 and 2018.
Collaborative distances:
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Bibliography
2018
IEEE J. Solid State Circuits, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.
IEEE J. Solid State Circuits, 2015
2014
19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory.
Proceedings of the Symposium on VLSI Circuits, 2012