Yanfeng Xu

Orcid: 0009-0003-6242-4239

According to our database¹, Yanfeng Xu authored at least 4 papers between 2019 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., March, 2024

2023

A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

2022

An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

2019

An Enhanced Time-Reversal Imaging Algorithm-Driven Sparse Linear Array for Progressive and Quantitative Monitoring of Cracks.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2019

Yanfeng Xu

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...