Yan Wang
Orcid: 0000-0003-4851-6113Affiliations:
- Tsinghua University, Institute of Microelectronics, Beijing, China
- Chinese Academy of Science, Beijing, China (PhD 1995)
According to our database1,
Yan Wang
authored at least 92 papers
between 2008 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A Broadband Bidirectional Four-Element Four-Beam Beamformer With Compact Floorplan in a 65nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025
2024
A Broadband Variable-Gain Low-Noise Amplifier With Low NF and Dual Phase Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024
Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
An Adaptive Analog Temperature Compensated W-Band Front-End With ±0.0033 dB/°C Gain Variation Across -30 °C to 120 °C.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
32.4 A 67.8-to-108.2GHz Power Amplifier with a Three-Coupled-Line-Based Complementary-Gain-Boosting Technique Achieving 442GHz GBW and 23.1% peak PAE.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 92%-Efficiency 0.828μs Settling Time FC5L Voltage Regulator Featuring Time-Domain Charge Balancing & Flying Capacitor Self-Switching for Wide Dynamic Range & Fast Transient Chiplet Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF Circuits.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Fast Surrogate-Assisted Constrained Multiobjective Optimization for Analog Circuit Sizing via Self-Adaptive Incremental Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Ka-Band Mutual Coupling Resilient Balanced PA with Magnetic Coupling Self-Cancelling Inductor Achieving 21.2dBm OP1dBand 27.6% PAE1dB.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
Asynchronous Parallel Expected Improvement Matrix-Based Constrained Multi-Objective Optimization for Analog Circuit Sizing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 1V 32.1 dBm 92-to-102GHz Power Amplifier with a Scalable 128-to-1 Power Combiner Achieving 15% Peak PAE in a 65nm Bulk CMOS Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Building Post-layout Performance Model of Analog/RF Circuits by Fine-tuning Technique.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
An Efficient Kriging-based Constrained Multi-objective Evolutionary Algorithm for Analog Circuit Synthesis via Self-adaptive Incremental Learning.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
14.5 A 1V W-Band Bidirectional Transceiver Front-End with <1dB T/R Switch Loss, <1°/dB Phase/Gain Resolution and 12.3% TX PAE at 15.1dBm Output Power in 65nm CMOS Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A K-Band Fractional-N PLL with Low-Spur Low-Power Linearization Circuit and PVT Robust Spur Trapper.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 2.8 nV/√ Hz Chopper Amplifier for Bridge Readout with Dual Ripple Reduction and Noise- Nonlinearity -Cancelling Loop.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Using Auto-Encoder Neural Networks for Memory Fault Tolerance in Gesture Recognition System.
Proceedings of the ICMAI 2021: 6th International Conference on Mathematics and Artificial Intelligence, Chengdu, China, March 19, 2021
Proceedings of the International Conference on IC Design and Technology, 2021
Proceedings of the International Conference on IC Design and Technology, 2021
Design and Optimization of N-type SiC Gate Turn-off Thyristor with High Turn-off Gain and High Breakdown Voltage.
Proceedings of the International Conference on IC Design and Technology, 2021
Sensitivity Importance Sampling Yield Analysis and Optimization for High Sigma Failure Rate Estimation.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
A Dual-Mode 24-32 GHz 4-Element Phased-Array Transceiver Front-End with SSA Beamformer for Autonomous Agile Unknown Signal Tracking and Blocker Rejection within <0.1 us and 21.3%/15% Transmitter Peak/OP1dB PAE.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
An Ultra-Compact 84.9-107GHz LNA with 4.9dB NF by Utilizing Coupled-line-based Gm-Boosting and Noise-Canceling Techniques in 65-nm CMOS Technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
Proceedings of the IVSP '20: 2nd International Conference on Image, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Adjoint Transient Sensitivity Analysis for Objective Functions Associated to Many Time Points.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IEEE Access, 2019
A Monolithic Dual-Band 77/94 GHz Transceiver Front-End With Shared Frequency Multiplier.
IEEE Access, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the ICIT 2019, 2019
Proceedings of the International Conference on IC Design and Technology, 2019
2018
Wideband Inductorless Low-Power LNAs with G<sub>m</sub> Enhancement and Noise-Cancellation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Study on scalability of hybrid junctionless FinFET and multi-stacked nanowire FET by TCAD simulation.
IEICE Electron. Express, 2018
Sci. China Inf. Sci., 2018
6 Gbps 16QAM fully integrated receiver using optimized neutralization technique LNA in 90 nm CMOS.
Sci. China Inf. Sci., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
An Accurate dB-Linear Programmable-Gain Amplifier with Temperature-Robust Characteristic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 3rd International Conference on Multimedia and Image Processing, 2018
Low-cost high-accuracy variation characterization for nanoscale IC technologies via novel learning-based techniques.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 60-GHz 360° 5-Bit Phase Shifter With Constant IL Compensation Followed by a Normal Amplifier With ±1 dB Gain Variation and 0.6-dBm OP<sub>-1dB</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Sci. China Inf. Sci., 2017
2016
J. Commun. Inf. Networks, 2016
A new Multi-Dose Method for extracting source/drain series resistances of halo-doped MOSFETs.
IEICE Electron. Express, 2016
A 3.1-4.2 GHz automatic amplitude control loop VCO with constant Kvco and <10mV amplitude variation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the Sixth International Conference on Image Processing Theory, 2016
2015
An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Behavioral Analysis and Optimization of CMOS CML Dividers for Millimeter-Wave Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Characterizing and optimizing human anticancer drug targets based on topological properties in the context of biological pathways.
J. Biomed. Informatics, 2015
A 64dB gain 60GHz receiver with 7.1dB noise figure for 802.11ad applications in 90nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 24GHz low power and low phase noise PLL frequency synthesizer with constant KVCO for 60GHz wireless applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Fast Convolution Method and Its Application in Mask Optimization for Intensity Calculation Using Basis Expansion.
IEEE Trans. Image Process., 2014
Scalable Compact Modeling for On-Chip Passive Elements with Correlated Parameter Extraction and Adaptive Boundary Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
A 3.45-4.22 GHz PLL frequency synthesizer with constant loop bandwidth for WLAN applications.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm<sup>2</sup> Die Size in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Single-Branch Third-Order Pole-Zero Low-Pass Filter With 0.014-mm<sup>2</sup> Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth-Power Scalability.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
An inductorless wideband low noise amplifier with current reuse and linearity enhancement.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Efficient Full-Chip Statistical Leakage Analysis Based on Fast Matrix Vector Product.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A unified model and direct extraction methodologies of various CPWs for CMOS mm-wave applications.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE Trans. Image Process., 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Understanding dynamic behavior of mm-wave CML divider with injection-locking concept.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A low-power ESD-protected 24GHz receiver front-end with π-type input matching network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Broadband compact model for on-chip mm-wave transformers and baluns with emphasis on capacitive coupling effects.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
High performance source optimization using a gradient-based method in optical lithography.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
A comprehensive model for gate delay under process variation and different driving and loading conditions.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Integr., 2009
2008
An effective parameter extraction method based on memetic differential evolution algorithm.
Microelectron. J., 2008
A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008