Yan Lin

According to our database, Yan Lin authored at least 23 papers between 2004 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

Statistical Timing and Power Optimization of Architecture and Device for FPGAs.

Lerong Cheng, Wenyao Xu, Fang Gong, Yan Lin, Ho-Yan Wong, Lei He

ACM Trans. Reconfigurable Technol. Syst., 2012

2008

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.

Yan Lin, Lei He, Mike Hutton

IEEE Trans. Very Large Scale Integr. Syst., 2008

Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.

Yu Hu, Yan Lin, Lei He, Tim Tuan

ACM Trans. Design Autom. Electr. Syst., 2008

Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.

Lerong Cheng, Yan Lin, Lei He

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007

Field Programmability of Supply Voltages for FPGA Power Reduction.

Fei Li, Yan Lin, Lei He

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Device and Architecture Cooptimization for FPGA Power Reduction.

Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Statistical placement for FPGAs considering.

Yan Lin, Mike Hutton, Lei He

IET Comput. Digit. Tech., 2007

Device and architecture concurrent optimization for FPGA transient soft error rate.

Yan Lin, Lei He

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.

Yan Lin, Lei He

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.

Yan Lin, Lei He

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.

Yan Lin, Lei He

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.

Yan Lin, Yu Hu, Lei He, Vijay Raghunat

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Placement and Timing for FPGAs Considering Variations.

Mike Hutton, Yan Lin, Lei He

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.

Yu Hu, Yan Lin, Lei He, Tim Tuan

Proceedings of the 43rd Design Automation Conference, 2006

2005

Circuits and architectures for field programmable gate array with configurable supply voltage.

Yan Lin, Fei Li, Lei He

IEEE Trans. Very Large Scale Integr. Syst., 2005

FPGA device and architecture evaluation considering process variations.

Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.

Yan Lin, Fei Li, Lei He

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.

Yan Lin, Lei He

Proceedings of the 42nd Design Automation Conference, 2005

Device and architecture co-optimization for FPGA power reduction.

Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He

Proceedings of the 42nd Design Automation Conference, 2005

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.

Yan Lin, Fei Li, Lei He

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Vdd programmability to reduce FPGA interconnect power.

Fei Li, Yan Lin, Lei He

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.

Fei Li, Yan Lin, Lei He, Jason Cong

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

FPGA power reduction using configurable dual-Vdd.

Fei Li, Yan Lin, Lei He

Proceedings of the 41th Design Automation Conference, 2004