Yajuan He

Orcid: 0000-0002-6081-313X

According to our database¹, Yajuan He authored at least 37 papers between 2005 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2024

131TOPS/W 8b ACIM Exploiting Weight-Embedded Auto-Accumulation and Supporting Symmetric Quantization Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

An 8T SRAM Based Digital Compute-In-Memory Macro For Multiply-And-Accumulate Accelerating.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Fast-Transient Right-Half-Plane Zero-Free Hybrid Buck-Boost Converter.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Design of Approximate Radix-256 Booth Encoding for Error-Tolerant Computing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021

Design of Ultra-Low Power Consumption Approximate 4-2 Compressors Based on the Compensation Characteristic.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Design of Approximate Multiplierless DCT with CSD Encoding for Image Processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Teaching Logic and Sequential Cell Characterization in Digital Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the ICETT 2021: 7th International Conference on Education and Training Technologies, Macau, China, April 14, 2021

2020

A Time-Efficient Automatic Circuit Approximation Method.

[BibT_eX]

[DOI]

Ziji Zhang

Yajuan He

Bo Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Subthreshold 10T SRAM Cell with Enhanced Read and Write Operations.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Design of an Energy-Efficient Approximate Compressor for Error-Resilient Multiplications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation.

[BibT_eX]

[DOI]

Ziji Zhang

Yajuan He

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Optimal Slope Ranking: An Approximate Computing Approach for Circuit Pruning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Disturb-Free 10T SRAM Cell with High Read Stability and Write Ability for Ultra-Low Voltage Operations.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Digital PID Based on Pseudo Type-III Compensation for DC-DC Converter.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A Probabilistic Prediction Based Fixed-Width Booth Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

A digital-assistant time-to-amplitude converter with dynamic range improvement.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Study on Simulation of Rice Yield with WOFOST in Heilongjiang Province.

[BibT_eX]

[DOI]

Shangjie Ma

Zhiyuan Pei

Yajuan He

Proceedings of the Computer and Computing Technologies in Agriculture X, 2016

2015

A pulse skipping modulation with adaptive duty ratio in buck converter application.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

A fast and energy efficient binary-to-pseudo CSD converter.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

The Methodology of Monitoring Crops with Remote Sensing at the National Scale.

[BibT_eX]

[DOI]

Proceedings of the Computer and Computing Technologies in Agriculture IX, 2015

Simulation of Winter Wheat Yield with WOFOST in County Scale.

[BibT_eX]

[DOI]

Proceedings of the Computer and Computing Technologies in Agriculture IX, 2015

2014

A digital calibration technique for multi-bit-per-stage pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Study on Survey Methods for Crop Area Change Reasons at National Scale.

[BibT_eX]

[DOI]

Proceedings of the Computer and Computing Technologies in Agriculture VIII, 2014

2013

Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC.

[BibT_eX]

[DOI]

Yajuan He

Bo Chen

Qiang Li

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2009

A New Redundant Binary Booth Encoding for Fast 2<sup>n</sup>-Bit Multiplier Design.

[BibT_eX]

[DOI]

Yajuan He

Chip-Hong Chang

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008

A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter.

[BibT_eX]

[DOI]

Yajuan He

Chip-Hong Chang

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2006

A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier.

[BibT_eX]

[DOI]

Yajuan He

Chip-Hong Chang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A novel covalent redundant binary Booth encoder.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An area efficient 64-bit square root carry-select adder for low power applications.

[BibT_eX]

[DOI]

Yajuan He

Chip-Hong Chang

Jiangmin Gu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Yajuan He

Timeline

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On csauthors.net:

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