Yajuan Du

Orcid: 0000-0002-8937-8055

According to our database1, Yajuan Du authored at least 37 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
GPU Performance Optimization via Intergroup Cache Cooperation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories.
ACM Trans. Archit. Code Optim., September, 2024

Extending SSD Lifetime via Balancing Layer Endurance in 3D NAND Flash Memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
LDPC Level Prediction Toward Read Performance of High-Density Flash Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics.
ACM Trans. Design Autom. Electr. Syst., 2023

Enhancing Polar Codes Efficiency on 3D Flash Memory by Exploiting Multiple Error Variations.
Proceedings of the 38th ACM/SIGAPP Symposium on Applied Computing, 2023

GPU Performance Acceleration via Intra-Group Sharing TLB.
Proceedings of the 52nd International Conference on Parallel Processing, 2023

Transparent File Deduplication with Reduced Update Cost on Encryption Enabled Mobile Devices.
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023

2022
Enhancing GPU Performance via Neighboring Directory Table Based Inter-TLB Sharing.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Work-in-Progress: Prediction-based Fine-Grained LDPC Reading to Enhance High-Density Flash Read Performance.
Proceedings of the International Conference on Compilers, 2022

Efficient Atomic Durability on eADR-Enabled Persistent Memory.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
Read-Ahead Efficiency on Mobile Devices: Observation, Characterization, and Optimization.
IEEE Trans. Computers, 2021

Layer-Aware Request Scheduling for 3D Flash-Based SSDs.
IEEE Access, 2021

Reducing tail latency of LSM-tree based key-value store via limited compaction.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

Stereo Superpixel Segmentation Via Dual-Attention Fusion Networks.
Proceedings of the 2021 IEEE International Conference on Multimedia and Expo, 2021

2020
TLFW: A Three-Layer Framework in Wireless Rechargeable Sensor Network with a Mobile Base Station.
Wirel. Commun. Mob. Comput., 2020

Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Static detection of real-world buffer overflow induced by loop.
Comput. Secur., 2020

Protecting the Intellectual Property of Deep Neural Networks with Watermarking: The Frequency Domain Approach.
Proceedings of the 19th IEEE International Conference on Trust, 2020

2019
Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Boosting read-ahead efficiency for improved user experience on mobile devices.
SIGBED Rev., 2019

United SSD block cleaning via constrained victim block selection.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC Reading.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

PreGC: Pre-migrating valid pages to relieve performance cliff of 3D solid-state drives: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2018
DigHR: precise dynamic detection of hidden races with weak causal relation analysis.
J. Supercomput., 2018

RBER Aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash Memory.
IEEE Access, 2018

BoundShield: Comprehensive Mitigation for Memory Disclosure Attacks via Secret Region Isolation.
IEEE Access, 2018

FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
A dynamic predictive race detector for C/C++ programs.
J. Supercomput., 2017

A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance.
ACM Trans. Embed. Comput. Syst., 2017

An empirical study of F2FS on mobile devices.
Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017

Improving read performance via selective Vpass reduction on high density 3D NAND flash memory.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Enhancing SSD performance with LDPC-aware garbage collection.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement.
Proceedings of the 54th Annual Design Automation Conference, 2017

A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017


  Loading...